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NJW4351
Unipolar Stepper Motor Driver
GENERAL DESCRIPTION The NJW4351 is a high efficiency DMOS unipolar stepper motor driver IC. Compared to previous devices, it is more suitable for low voltage operation, capable of handling 5.0V, 3.3V and the like logic circuits. Drive Stage consists of DMOS which produces high efficiency and low heat generation motor drive circuit. The motor can be controlled by the STEP and DIR system. Further more, to improve controllability of system, MO, ENABLE, RESET and PD function are included, various applications are possible. FEATURES * Supply Voltage PACKAGE OUTLINE
NJW4351VC3
NJW4351D
VDD=2.7 to 5.5V VMM= to 55V * Output Current Io=1.5A peak at VDD=5V * Low Quiescent Current IDD=500A typ. * STEP&DIR Input Operation (Internal Translator) * HALF/FULL Mode Generation * TTL compatible Input With Schmitt-Comparator * ENABLE Function * RESET Function * MO (Motor Origin Monitor) -Position-indication Output * PD (Standby) Function * Under Voltage Lock Out * Thermal Shutdown Circuit * Alarm Output Function (As the protection circuit operates) * BCD Technology * Package Outline SSOP20-C3, DIP16
BLOCK DIAGRAM
VDD
NJW4351
POWER ON RESET
OUT2B OUT2A
HSM STEP DIR RESET
GATE DRIVE
OUT1B OUT1A
TRANSLATOR
ENABLE PD
Bias Circuit
MO ALARM
UNDER VOLTAGE LOCK OUT
SENSE1
THERMAL SHUT DOWN
SENSE2
GND
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NJW4351
PIN CONNECTION
PD VDD HSM STEP DIR RESET ENABLE MO ALARM GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 N.C. N.C. OUT1A SENSE1 OUT1B OUT2B SENSE2 OUT2A N.C. N.C. VDD 1 HSM 2 STEP 3 DIR 4 RESET 5 ENABLE 6 MO 7 ALARM 8 16 PD 15 OUT1A 14 SENSE1 13 OUT1B 12 OUT2B 11 SENSE2 10 OUT2A 9 GND
SSOP20-C3 PIN FUNCTION LIST
Pin#
DIP16
SSOP20-C3 1 2 3 4 5 6 7 8 9 10 11,12,19,20 13 14 15 16 17 18
DIP16 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Terminal Name
Function Power Saving State Setting Input Terminal Logic Voltage Supply Terminal HALF/FULL Step Mode Setting Input Terminal Stepping Pulse Input Terminal Direction Setting Input Terminal Reset Input Terminal Phase Output Off Input Terminal MO Output Terminal Internal Protection Operation Detection Output Terminal Logic Ground Terminal No Connection 2ch Output Terminal A Current Detection Resistance Connection Terminal 2 2ch Output Terminal B 1ch Output Terminal B Current Detection Resistance Connection Terminal 1 1ch Output Terminal A
Remark L=Standby, H=Normal Operation Logic Voltage Supply L=FULL, H=HALF The Translator is triggered by positive edge of STEP Pulse. L=FORWARD, H=REVERSE L=The Translator is initialized, H=Normal Operation L=ACTIVE, H=Normal Operation When the Translator is in initial status, L level is to output. When the internal protection operation is detected, L level is to output. Logic Ground No Connection It connects resistance for the detection of the side of 2ch. At the unused time, it connects with GND. It connects resistance for the detection of the side of 1ch. At the unused time, it connects with GND.
PD VDD HSM STEP DIR RESET ENABLE MO ALARM GND N.C. OUT2A SENSE2 OUT2B OUT1B SENSE1 OUT1A
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NJW4351
UNIT V VDD PIN V OUT1A/1B/2A/2B PIN STEP, DIR, HSM, RESET, Logic Input Voltage VIN 7 V ENABLE, PD PIN ALARM Output Voltage VALARM 7 V ALARM PIN MO Output Voltage VMO 7 V MO PIN Output Current Io 1.5 A OUT1A/1B/2A/2B PIN ALARM Output Current IALARM 20 mA ALARM PIN MO Output Current IMO 20 mA MO PIN Operating Temperature Topr -40 to +85 C Junction Temperature Tj -40 to +150 C Storage Temperature Tstg -50 to +150 C Power Dissipation 1.0 W (*1) Mounted on 2Layers PCB PD (SSOP20-C3) 1.5 W (*1) Mounted on 4Layers PCB 1.2 W Device itself Power Dissipation PD 1.4 W (*1) Mounted on 2Layers PCB (DIP16) 2.0 W (*1) Mounted on 4Layers PCB (*1): Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers/4Layers) RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITION Logic Supply Voltage VDD VDD=5V Output Current Io VDD=3.3V (Ta=25C) MAX. UNIT 5.5 V mA 500 mA ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Logic Supply Voltage VDD Motor Output Voltage VO (Ta=25C) RATINGS 7 55
MIN. 2.7 -
TYP. 3.3 500 -
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NJW4351
ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL GENERAL
Quiescent current IDD
(VMM=24V, VDD=PD=3.3V, RL=1k, RMO=3.3k, RALARM=3.3k, Ta=25C) TEST CONDITION MIN. TYP. MAX. UNIT
STEP,DIR,HSM,RESET,ENABLE=3.3V, Except IIH
2.0 0 0.4 2.4 0 0.4 15 2 2.0 0 2.4 0 15 -200 2 1 1 1.6 1.9 0.2
0.5 0.55 0.55 33 10 100 0.13 0.14 33 0 100 1.2 0.9 1 0.3 0.3 0.3 170 140 30 1.9 2.2 0.3
0.8 1.0 0.8 0.8 45 20 0.8 0.8 45 +200 1.45 1.25 5 1 0.5 1 0.5 1 2.2 2.5 0.4
mA uA V V V V V V uA uA k us V V V V V V uA nA k us us us uA us uA V uA V uA C C C V V V
Quiescent current (Standby) IPD PD=0V, except IIH INPUT BLOCK1 (STEP) H level input voltage1 VIH1 L level input voltage1 VIL1 Input hysteresis voltage1 VIHYS1 H level input voltage2 VIH2 VDD=5V L level input voltage2 VIL2 VDD=5V Input hysteresis voltage2 VIHYS2 VDD=5V H level input current IIH STEP=3.3V L level input current IIL STEP=0V Input pull down resistance RDOWN Input pulse widths tp INPUT BLOCK2 (PD/DIR/HSM/RESET/ENABLE) H level input voltage1 VIH1 L level input voltage1 VIL1 Input hysteresis voltage1 VIHYS1 H level input voltage2 VIH2 VDD=5V L level input voltage2 VIL2 VDD=5V Input hysteresis voltage2 VIHYS2 VDD=5V H level input current L level input current IIH IIL
PD, DIR, HSM, RESET, ENABLE=3.3V, per input PD, DIR, HSM, RESET, ENABLE=0V, per input
Input pull down resistance RDOWN Input pulse widths tp Data setup time tDS Data hold time tDH MOTOR OUTPUT BLOCK (OUT1A/OUT1B/OUT2A/OUT2B) Output ON resistance1 RO1 Io=500mA Output ON resistance2 RO2 VDD=5.0V, Io=500mA Output leak current IOLEAK ENABLE=0V,Vo=50V Delay time tDELAY At turn on Sense terminal leak current ISENSELEAK ENABLE=0V, VSENSE=1V(SENSEGND) MO OUTPUT (MO) L level output voltage VMO IMO=10mA MO terminal leak current IMOLEAK VMO=5.5V MO OUTPUT (ALARM) L level output voltage VALARM IALARM=10mA ALARM terminal leak current IALARMLEAK VALARM=5.5V THERMAL SHUTDOWN BLOCK Thermal shutdown operating TTSD1 temperature Thermal shutdown recovery TTSD2 temperature Thermal shutdown hysteresis TTSD UNDER VOLTAGE LOCK OUT BLOCK UVLO operating voltage VUVLO1 UVLO recovery voltage VUVLO2 UVLO hysteresis voltage VUVLO
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NJW4351
PIN/ CIRCUIT OPERATIONAL DEFINITION Logic Input Pins Operational Voltage Definition
At VDD=3.3V
VIN VDD
H level input voltage
V 5.0V
H level input voltage
2.0V
2.0V VHYS
0.8V
L level input voltage
0.8V
L level input voltage
0V
Logic Input Pins Timing Definition
At VDD=3.3V Master Pin STEP V VIH=2.0V VIL=0.8V
0V
L level
H level
L lebvel
H level
L level
tp
tp
Slave Pins HSM, DIR RESET, PD VIH=2.0V VIL=0.8V
tp
tp
tDS1
tDH2
tDS2
tDH1
t
Data Setup Time and Data Hold Time are defined to positive edge of STEP. tDS1,tDS2=Data Setup Time, tDH1,tDH2=Data Hold Time tDS1,tDH1=HSM,DIR,RESET, PD, tDS2,tDH2=HSM,DIR
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NJW4351
Thermal Shutdown Operational Definition
TSD Recovery TEMP (Normal Operation)
Hysteresis TEMP
TSD Operating TEMP (Output Suspention)
-40C
140C 150C 170C
(Tj max)
Tj
Under Voltage Protection Operational Definition
VDD 5.5V 2.7V 2.1V 1.9V 0V
Recommended Operating Maximum Voltage
Recommended Operating Minimum Voltage UVLO Recovery Voltage(Normal Operation) Hysteresis Voltage UVLO Operating Voltage(Output Suspention)
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NJW4351
TERMINAL STATUS
STEP-Motor Stepping Pulse Input STEP Negative Edge Positive Edge OPEN Function Internal translator gose on every this edge MO-Motor Origin Position Output MO H L Function The translator is in noninitial status The translator is in initial status
HSM-HALF/FULL Step Mode Input HSM H L OPEN Function HALF Step FULL Step FULL Step (Inside PULL DOWN)
ALARM-Alarm Output ALARM H L Function Normal Operation OUT terminals are OFF, as the protection circuit operates.
DIR-Direction Command Input DIR H L OPEN Function REVERSE FORWARD FORWARD (Inside PULL DOWN) ENABLE-Enable Input ENABLE H L OPEN Function ACTIVE OUT terminals are OFF , but internal logic circuit is ON. OUT terminals are OFF , but internal logic circuit is ON. (Inside PULL DOWN) RESET-Reset Input RESET H L OPEN Function ACTIVE RESET RESET (Inside PULL DOWN)
PD-Power Down State Input PD H L OPEN Function ACTIVE RESET+POWER SAVING RESET+POWER SAVING (Inside PULL DOWN)
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NJW4351
TIMING CHART
POR 1 2 3 4 1 2 3 4 1
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
L H H L L OFF ON OFF ON ON
STEP OUT2B OUT2A OUT1B OUT1A MO
After POR OFF ON OFF ON ON
1 OFF ON ON OFF OFF
2 ON OFF ON OFF OFF
3 ON OFF OFF ON OFF
4 OFF ON OFF ON ON
MO
Fig.1 Full Step Mode / Forward Direction Sequence
POR 1 2 3 4 1 2 3 4 1
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
H H H L L OFF ON OFF ON ON
STEP OUT2B OUT2A OUT1B OUT1A MO
After POR OFF ON OFF ON ON
1 ON OFF OFF ON OFF
2 ON OFF ON OFF OFF
3 OFF ON ON OFF OFF
4 OFF ON OFF ON ON
MO
Fig.2 Full Step Mode / Reverse Direction Sequence
POR 1 2 3 4 5 6 7 8 1
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
L H H H L OFF ON OFF ON ON
STEP OUT2B OUT2A OUT1B OUT1A MO
After POR OFF ON OFF ON ON
1 OFF ON OFF OFF OFF
2 OFF ON ON OFF OFF
3 OFF OFF ON OFF OFF
4 ON OFF ON OFF OFF
5 ON OFF OFF OFF OFF
6 ON OFF OFF ON OFF
7 OFF OFF OFF ON OFF
8 OFF ON OFF ON ON
MO
Fig.3 Half Step Mode / Forward Direction Sequence
POR 1 2 3 4 5 6 7 8 1
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
H H H H L OFF ON OFF ON ON
STEP OUT2B OUT2A OUT1B OUT1A MO
After POR OFF ON OFF ON ON
1 OFF OFF OFF ON OFF
2 ON OFF OFF ON OFF
3 ON OFF OFF OFF OFF
4 ON OFF ON OFF OFF
5 OFF OFF ON OFF OFF
6 OFF ON ON OFF OFF
7 OFF ON OFF OFF OFF
8 OFF ON OFF ON ON
MO
Fig.4 Half Step Mode / Reverse Direction Sequence
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NJW4351
POR 1 2 3 4 1 2 3 4 1
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
L H H L L OFF ON OFF ON ON
* When ENABLE is active OUT terminals are OFF, but internal logic circuit is ON.
MO
Fig.5 Full Step Mode / Enable Sequence
POR 1 2 3 4 5 6 7 8 1
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
L H H H L OFF ON OFF ON ON
* When ENABLE is active OUT terminals are OFF, but internal logic circuit is ON.
MO
Fig.6 Half Step Mode / Enable Sequence
POR 1 2 * * * 1 2 3 4
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
L H H L L OFF ON OFF ON ON
* When RESET is active OUT terminals are OFF, and internal logic circuit is to reset.
MO
Fig.7 Full Step Mode / Reset Sequence
POR 1 2 * * * 1 2 3 4
DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
L H H H L OFF ON OFF ON ON
* When RESET is active OUT terminals are OFF, and internal logic circuit is to reset.
MO
Fig.8 Half Step Mode / Rest Sequence
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NJW4351
POR 1 2 * * * 1 2 3 4
PD DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
H L H H L L OFF ON OFF ON ON
* When PD is active it forces all settings to initialize and be in stand-by mode, and MO is to be low.
MO
Fig.9 Full Step Mode / PD Sequence
POR
1
2
*
*
*
1
2
3
4
PD DIR ENABLE RESET HSM STEP OUT2B OUT2A OUT1B OUT1A
H L H H H L OFF ON OFF ON ON
* When PD is active it forces all settings to initialize and be in stand-by mode, and MO is to be low.
MO
Fig.10 Full Step Mode / PD Sequence
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NJW4351
FUNCTION DESCRIPTION The NJW4351 is designed for a high-performance constant-voltage unipolar stepper motor. Using a general-purpose STEP&DIR motion controller, the device can easily control a stepper motor when combined with a pulse generator. The maximum value of the phase output is 55 V that keeps the voltage margin of the motor from exceeding the limit, which is a common problem with unipolar winding systems. It simplifies the design of power control circuits during phase turn-off. LOGIC INPUT BLOCK All inputs are LS-TTL compatible. Input Block1 (STEP) has Schmitt Comparator to keep the thresh voltage unchanged even if logic supply voltage applied to it varies. It produces hesteresis voltage for noise immunity. Input Block2 (PD, DIR, HSM, RESET, ENABLE) has Schmitt Inverter for the main purpose of noise immunity. Inputs are internally connected to GND by pull-down resistances, being open, the device recognizes to be low. * STEP - Stepping Pulse The Translator starts counting on every positive edge of the STEP. In full step mode, the pulse turns the stepper motor at the basic step angle. In half step mode, two pulses are required to turn the motor at the basic step angle. The DIR (direction) signal and HSM (half/full mode) are latched to the STEP positive edge and must therefore be established before the start of the positive edge. * DIR - Direction The DIR signal determines the step direction. The direction of the stepper motor depends on how the NJW4351 is connected to the motor. DIR can be modified anytime, it miss-steps when it is simultaneous with the positive edge. * HSM - Half/full Step Mode Switching This signal determines whether the stepper motor runs at half step or full step mode. The Translator is set to half step mode when HSM is low. Like DIR, HSM can be modified anytime but not when its simultaneous with the positive edge. * ENABLE - Phase Output Off All phase outputs are turned off when ENABLE goes high reducing power consumption. * RESET A two-phase stepper motor repeats the same winding energizing sequence every angle that is a multiple of four of the basic step. The Translator is repeated every four pulses in full step mode and every eight pulses in half step mode. When RESET is low, the Translator is initialized and the phase outputs turn-off. When returning to high, the phase outputs are set to the initial energizing pattern output status. * PD-Power Down When PD goes low, it forces all settings to initialize and be in stand-by mode. AND MO is to be low.
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NJW4351
POR - Power On And Reset Function The POR connected to VDD is to prevent miss-step under unstable condition of the inputting of logic supply voltage VDD. After inputting VDD, the phase outputs are set to the initial energizing pattern output status. PHASE OUTPUT BLOCK The phase output block consists of four open-drain DMOS FET capable of sinking max 1.5A. MO - Motor Origin Monitor In initialized position of the Translator, MO output low to indicate to external devices that it is the initial energizing pattern output status.
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NJW4351
PRECAUTIONS 1. Never disconnect the device or PC-board when power is supplied. 2. Remember that excessive voltages might be generated by motor, even though clamping diodes are used. 3. Choose a motor that is proportional to the current you need to establish desired torque. A high supply voltage will gain better stepping performance. If the motor is not specified for the VMM voltage, a current limiting resistor will be necessary to connect in series with center tap. This changes the L/R time constant. 4. Avoid VMM and VDD power supplies with serial diodes (without filter capacitor) and common ground with VDD. 5. To change actual motor rotation direction, exchange motor connections at OUT1A and OUT1B (OUT2A and OUT2B). 6. Half-stepping In the half-step mode, the power input to the motor alternates between one or two phase windings. In half-step mode, motor resonances are reduced. In a two-phase motor, the electrical phase shift between the windings is 90 degrees. The torque developed is the vector sum of two windings energized. Therefore, when only one winding is energized, which is the case in half-step mode for every second step, the torque of the motor is reduced by approximately 30%. This causes a torque ripple. 7. Drive Circuits High-performance stepper motor operation requires windings to be energized immediately at phase turn-on and quickly turned off when not in use. 8. Phase Turn-off Considerations When the winding current is turned off, induced high voltage spike will damage the drive circuits if not properly suppressed. Refer to the turn-off circuits described in Figures 11 to 14. The voltage potential at the phase output terminal may sometimes become negative (GND or below) due to the configuration of the turn-off circuit or the kickback voltage generated in it. In this condition there is a danger of a malfunction occurring in the logic circuit inside the device. 8.1. Precautions against high voltage using the Zener-diode turn-off circuit Refer the Zener-diode turn-off circuit (see Fig.15). Zener-diode voltage value is Vz and the forward voltage of the diodes connected in series with the Zener-diode is Vd, the voltage VP of the phase output (OUT1A, OUT1B, OUT2A, OUT2B) terminal when the turn-off operation have occurred is expressed by the following equation. VP = VMM - (Vz + Vd) The higher voltage, Vz, used, the shorter is the turn-off time of the winding current, thus producing high speed operation of the stepper motor. Note, however, that depending on the Zener voltage, VZ, the voltage potential at the phase output terminal may become negative, so design the turn-off circuit as indicated below. 8.1.1. When VP is a positive voltage: VMM > VZ + Vd The circuit configuration is that of Fig.15. Set the Zener voltage. For example, if VMM is 12 V, VZ + Vd is no higher than12V. 8.1.2 When VP is a negative voltage: VMM < VZ + Vd The circuit configuration is that of Fig.16. In order to prevent a malfunction due to a negative voltage, be sure to insert diodes in series with the phase output terminals.
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NJW4351
VMM
i
R VMM i
Fig.11 Diode and turn off circuit.
Fig12 Resistor and turn off circuit.
VMM
VZ i
VMM
i
VZ
Fig.13 Zener diode and turn off circuit.
Fig.14 Power regeneration and turn off circuit.
Turn off circuit
(case of zener diode)
Negative voltage prevention diode
Turn off circuit
(case of zener diode)
VMM
VZ
VMM
VZ
Vd
Fig.15 Zener diode and turn off circuit 2.
Fig.16 Turn off negative voltage prevention circuit by zener diode
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NJW4351
APPLICATION CIRCUIT
VDD
+ +
VMM
RMO
RALARM
VDD
NJW4351
Micro controller/ Microprocessor
output output output output HSM STEP DIR RESET
GATE DRIVE POWER ON RESET
OUT2B OUT2A OUT1B OUT1A
TRANSLATOR
output output input input
ENABLE PD
Bias Circuit
MO ALARM
UNDER VOLTAGE LOCK OUT
SENSE1
THERMAL SHUT DOWN
SENSE2
GND
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NJW4351
TYPICAL CHARACTERISTICS
IDD - VDD STEP=HSM=DIR=RESET=ENABLE=PD=VDD, Ta=25oC RON - VDD Io=500mA, Ta=25oC
1.0 0.9 0.8
4.0 3.5 3.0
0.7 IDD [mA] RON [] 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.6 0.5 0.4 0.3 1.0 0.2 0.1 0.0 VDD [V] 0.5 0.0 0 1 2 3 VDD [V] 4 5 6 7 2.5 2.0 1.5
RON1 - Io VDD=3.3V, Ta=25oC
RON2 - Io VDD=5.0V, Ta=25oC
2.0 1.8 1.6 1.4 RON1 [] RON2 [] 0 100 200 Io [mA]
Pd - Io VDD=3.3V,Ta=25oC 1 0.9 0.8
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 300 400 500 0 250 500 750 Io [mA]
Pd - Io VDD=5.0V,Ta=25oC 9 8 7
1.2 1.0 0.8 0.6 0.4 0.2 0.0
1000
1250
1500
0.7 6 0.6
Pd [W]
0.5 0.4 0.3
Pd [W]
5 4 3
Two channels on
0.2 0.1 0 0 100 200 Io [mA] 300 400 500 2
Two channels on
One channel on
1 0 0 250 500 750 Io [mA] 1000
One channel on
1250 1500
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NJW4351
TYPICAL CHARACTERISTICS
VOR - Io VDD=3.3V, ENABLE=0V,Ta=25oC 1.2 1.1 1.0 0.9 0.8 0.5 VMO [V] VOR [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 250 500 750 Io [mA] 1000 1250 1500 0.0 0 5 10 IMO [mA] 15 20 0.2 0.1 0.4 0.3 0.7 0.6 0.8 VMO - IMO VDD=3.3V, RESET=0V,Ta=25oC
RON1 - Tj VDD=3.3V, Io=500mA 3.0 2.8 2.6 2.4 2.2 2.0 RON1 [] RON2 [] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 Tj [deg.C] IDD1 - Tj VDD=3.3V 1.0 0.9 0.8 0.7 IDD1 [mA] 0.6 VOR [V] 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25 0 25 50 Tj [deg.C] 75 100 125 150 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25 0 75 100 125 150 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0
RON2 - Tj VDD=5.0V, Io=500mA
25
50 Tj [deg.C]
75
100
125
150
VOR - Tj VDD=3.3V,Io=500mA
25
50 Tj [deg.C]
75
100
125
150
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NJW4351
TYPICAL CHARACTERISTICS
VMO - Tj VDD=3.3V,IMO=10mA 0.8 0.7 0.6 0.5 VMO [V] 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 Tj [deg.C] 75 100 125 150
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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Ver.2010-03-26

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